MOS-gated power device with doped polysilicon body and process for forming same

ABSTRACT

An improved MOS-gated power device 300 with a substrate 101 having an upper layer 101 a  of doped monocrystalline silicon of a first conduction type that includes a doped well region 107 of a second conduction type. The substrate further includes at least one heavily doped source region 111 of the first conduction type disposed in a well region 107 at an upper surface of the upper layer, a gate region 106 having a conductive material 105 electrically insulated from the source region by a dielectric material, a patterned interlevel dielectric layer 112 on the upper surface overlying the gate and source regions 114, and a heavily doped drain region of the first conduction type 115. The improvement includes body regions 301 containing heavily doped polysilicon of the second conduction type disposed in a well region 107 at the upper surface of the monocrystalline substrate.

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application is a divisional application of U.S. Patent Application Ser. No. 09/731,169, filed Dec. 6, 2000 (Attorney Docket No. 90065.144500/SE-1649PD).

FIELD OF THE INVENTION

[0002] The present invention relates to semiconductor devices and, more particularly, to an MOS-gated power device having a doped polysilicon body and to a process for forming the device

BACKGROUND OF THE INVENTION

[0003]FIG. 1 schematically depicts the cross-section of a trench MOS-gated device 100 of the prior art formed on an upper layer 101 a of an N+substrate 101. Device 100 includes a trench 102 whose sidewalls 103 and floor 104 are lined with a gate dielectric such as silicon dioxide. Trench 102 is filled with a conductive material 105 such as doped polysilicon, which serves as an electrode for gate region 106.

[0004] Upper layer 101 a of substrate 101 further includes P-well regions 107 overlying an N-drain zone 108. Disposed within P-well regions 107 at an upper surface 109 of upper layer 101 a are heavily doped P+body regions 110 and heavily doped N+source regions 111. An interlevel dielectric layer 112 is formed over gate region 106 and source regions 111. Contact openings 113 enable metal layer 114 to contact body regions 110 and source regions 111. A drain metal layer 115 is applied to the rear surface of N+substrate 101.

[0005]FIG. 2 is a schematic cross-sectional view of a vertical planar MOSFET device 200 of the prior art formed on an upper layer 101 a of an N+substrate 101. Device 200 includes a planar gate region 201 comprising a gate dielectric layer 202, silicon oxide, for example, and a conductive layer 203, doped polysilicon, for example, that serves as a gate electrode.

[0006] Device 200 resembles device 100 in that upper layer 101 a further includes P-well regions 107 overlying an N-drain zone 108, and heavily doped P+body regions 110 and heavily doped N+source regions 111 disposed within P-well regions 107 at upper surface 109 of upper layer 101 a. An interlevel dielectric layer 112 is formed over gate region 201 and source regions 111, and contact openings 113 enable metal layer 114 to contact body and source regions 110 and 111 , respectively. A drain metal layer 115 is applied to the rear surface of N+substrate 101. The body and source regions of devices currently in common use, for example, structures 100 and 200 depicted in FIGS. 1 and 2, respectively, are typically formed by successive implantation and diffusion of dopants of opposite conduction type into a semiconductor substrate, a procedure that requires the use of two photoresist masks, one for the source, the other for the body. Lateral diffusion of dopants, high energy implantation scatter during body formation, and allowance for possible misalignment are factors that adversely affect efforts to reduce the size of the device. There is a need for power devices of reduced size relative to those in current use the present invention meets this need.

SUMMARY OF THE INVENTION

[0007] The present invention is directed to an improved MOS-gated power device on a substrate having an upper layer of doped monocrystalline silicon of a first conduction type that includes a doped well region of a second conduction type. The substrate further comprises at least one heavily doped source region of the first conduction type disposed in the well region at an upper surface of the upper layer, a gate region comprising a conductive material electrically insulated from the source region by a dielectric material, a patterned interlevel dielectric layer on the upper surface overlying the gate and source regions, and a heavily doped drain region of the first conduction type. The improvement comprises: body regions comprising heavily doped polysilicon of the second conduction type disposed in the well region at the upper surface of the monocrystalline silicon substrate.

[0008] The invention is further directed to a process for forming an MOS-gated power device that comprises: providing a substrate having an upper layer of doped monocrystalline silicon of a first conduction type that includes a doped well region of a second conduction type. The substrate further comprises a heavily doped source regions of the first conduction type disposed in the well region at an upper surface of the upper layer, a gate region comprising a conductive material electrically insulated from the source region by a dielectric material, heavily doped drain region of the first conduction type, a patterned interlevel dielectric layer on the upper surface overlying the gate and source regions.

[0009] The process further comprises: forming a body mask on the substrate, and selectively removing portions of the source region and underlying well region remotely disposed from the gate region, thereby forming at least one body hollow in the substrate; removing the body mask, and forming a blanket layer of heavily doped polysilicon of the second conduction type that overlies the substrate and interlevel dielectric layer and fills the body hollow; selectively removing portions of the polysilicon blanket layer from the source region and interlevel dielectric layer, leaving heavily doped polysilicon filling the body hollow and thereby forming a body region; depositing over the upper surface and interlevel dielectric layer a source metal layer in electrical contact with the source and body regions; and forming a drain metal layer in contact with the drain region in the substrate.

BRIEF DESCRIPTION OF THE DRAWINGS

[0010]FIGS. 1 and 2 schematically depict cross-sections of, respectively, a trench MOS-gated and a vertical planar MOS device of the prior art.

[0011]FIGS. 3 and 4 are schematic cross-sectional representations of, respectively, a trench MOS-gated and a vertical planar MOS device in accordance with the present invention.

[0012] FIGS. 5A-D depict a process for forming a trench MOS-gated power device of the present invention.

[0013]FIG. 6 is a schematic cross-sectional representation of a lateral MOSFET in accordance with the present invention.

DETAILED DESCRIPTION OF THE INVENTION

[0014] In FIG. 3 is schematically depicted the cross-section of a trench MOS-gated device 300 of the present invention formed on an upper layer 101 a of an N+substrate 101. As with device 100 of the prior art, device 300 includes a trench 102 whose sidewalls 103 and floor 104 are lined with a gate dielectric such as silicon dioxide. Trench 102 is filled with a conductive material 105 such as doped polysilicon, which serves as an electrode for gate region 106.

[0015] Upper layer 101 a of substrate 101 further includes P-well regions 107 overlying an N-drain zone 108. Disposed within P-well regions 107 at an upper surface 109 of upper layer 101 a are heavily doped N+source regions 111. Also disposed at upper surface 109 within P-well regions 107 are P+body regions 301 comprising, in accordance with the present invention, heavily doped polysilicon. Device 300 further includes interlevel dielectric layer 112, contact openings 113, source metal layer 114, and drain metal layer 115, corresponding to those elements in prior art device 100.

[0016]FIG. 4 schematically illustrates a planar MOSFET device 400 of the present invention formed on an upper layer 101 a of an N+substrate 101 and including a planar gate region 201 comprising a gate dielectric layer 202, silicon oxide, for example, and a conductive layer 203, doped polysilicon, for example, that serves as a gate electrode. Planar device 400 resembles prior art device 200 in that upper layer 101 a further includes P-well regions 107 overlying an N-drain zone 108, and heavily doped N+source regions 111 disposed within P-well regions 107 at upper surface 109 of upper layer 101 a. Also disposed at upper surface 109 within P-well regions 107 are P+body regions 401 comprising, in accordance with the present invention, heavily doped polysilicon. Device 400 further includes interlevel dielectric layer 112, contact openings 113, source metal layer 114, and drain metal layer 115, corresponding to those elements in prior art device 200.

[0017] Although FIGS. 3 and 4 each show only one MOSFET, devices currently employed in the industry consist of an array of such devices having striped open-cell or closed-cell topology.

[0018] In FIGS. 5A-D is depicted a process for making trench MOS-gated device 300 of the present invention. FIG. 5A depicts a structure, obtained by procedures standard in the industry, having a substrate 101 that includes an upper layer 101 a, preferably an epitaxial layer, in which is formed P-well regions 107 and a gate trench region 106 comprising a trench 102 lined with dielectric sidewalls 104 and floor 103 and substantially filled with a semiconductor material 105. An N+dopant is implanted and driven to form blanket N+source regions 111 a, and a patterned interlevel dielectric layer 112 is formed on substrate 101.

[0019] As shown in FIGS. 5B and 5C, a photoresist mask (not shown) is employed to dimple etch portions of N+blanket source regions 111 a and P-well regions 107, and, following removal of the mask, a blanket layer 301 a of heavily doped polysilicon is formed on interlevel dielectric layer 112 and substrate 101, filling the hollows 501 produced by the etching of regions 111 a and 107.

[0020]FIG. 5D depicts the controlled etching of highly doped polysilicon blanket layer 301 a, leaving body regions 301 comprising heavily P+doped polysilicon adjacent N+source regions 111. Deposition of source metal layer 114 and drain metal layer 115 completes the fabrication of device 300, as shown in FIG. 3.

[0021] Because it avoids a source photoresist masking step and its required misalignment tolerance allowance, and further avoids possible lateral diffusion of dopants and high energy implantation scatter during body formation, the process of the present invention provides for the formation of very narrow body regions 301 compared with body regions 110 in device 100, resulting in a device 300 of reduced size relative to that of prior art devices.

[0022] Variations of the described specific process flow are contemplated as being within the present invention. For example, the process depicted in FIGS. 5A-D for the fabrication of trench MOS-gated device 300 can be applied to form planar MOS device 400 of the present invention.

[0023]FIG. 6 schematically depicts a lateral MOSFET 600 of the present invention formed on an upper layer 101 a of a P+substrate 601, which may optionally include an N+buried layer (not shown) located beneath upper layer 101 a. Device 600 includes a gate region 601 comprising a gate dielectric layer 602, silicon oxide, for example, and a conductive layer 603, doped polysilicon, for example, that serves as a gate electrode. Lateral device 600 further includes a P-well region 604 and heavily doped N+source and drain regions 605 and 606, respectively, disposed at upper surface 109 of upper layer 101 a, source region 605 being situated within P-well region 604. Also disposed at upper surface 109 within P-well region 604 is a P+body region 607 comprising, in accordance with the present invention, heavily doped polysilicon. Device 600 further includes interlevel dielectric layer 608, and source and drain metal layers 609 and 610, respectively, which are in contact with source and drain regions 605 and 606, respectively.

[0024] Although the embodiments described above relate to MOS power devices, one skilled in the art may adapt the present invention to other devices, including insulated gate bipolar transistors and MOS-controlled thyristors.

[0025] The invention has been described in detail for the purpose of illustration, but it is understood that such detail is solely for that purpose, and variations can be made therein by those skilled in the art without departing from the spirit and scope of the invention, which is defined by the EXHIBIT A Pat # APl # Status Country Title 4975751 253437 Granted US HIGH BREAKDOWN ACTIVE DEVICE STRUCTURE WITH LOW SERIES RESISTANCE 5091336 07/592308 Granted US HIGH BREAKDOWN ACTIVE DEVICE STRUCTURE WITH LOW SERIES RESISTANCE 4651179 749091 Granted US LOW RESISTANCE GALLIUM ARSENIDE FIELD EFFECT TRANSISTOR 4750666 853255 Granted US METHOD OF FABRICATING GOLD BUMPS ON IC'S AND POWER CHIPS 4441117 287497 Granted US MONOLITHICALLY MERGED FET AND BIPOLAR JUNCTION TRANSISTOR 4749886 916869 Granted US REDUCED PARALLEL EXCLUSIVE OR AND EXCLUSIVE NOR GATE 4857977 88353 Granted US LATERAL METAL-OXIDE-SEMICONDUCTOR CONTROLLED TRIACS 4847671 51424 Granted US MONOLITHICALLY INTEGRATED INSULATED GATE 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POTTED TRANSDUCER ARRAY WITH MATCHING NETWORK IN A MULTIPLE PASS CONFIGURATION 09/663235 Pending US POTTED TRANSDUCER ARRAY WITH MATCHING NETWORK IN A MULTIPLE PASS CONFIGURATION 6077744 09/255092 Granted US SEMICONDUCTOR TRENCH MOS DEVICES 09/037723 Pending US METHODS FOR MAKING SEMICONDUCTOR DEVICES BY LOW TEMPERATURE DIRECT BONDING 09/296472 Pending US FAST TURN-OFF POWER SEMICONDUCTOR DEVICES 6153495 09/036815 Granted US ADVANCED METHODS FOR MAKING SEMICONDUCTOR DEVICES BY LOW TEMPERATURE DIRECT BONDING 09/036838 Pending US DEVICES FORMABLE BY LOW TEMPERATURE DIRECT BONDING 6137139 09/324553 Granted US LOW VOLTAGE DUAL-WELL MOS DEVICE HAVING HIGH RUGGEDNESS, LOW ON-RESISTANCE, AND IMPROVED BODY DIODE REVERSE RECOVERY 6104062 09/107721 Granted US SEMICONDUCTOR DEVICE HAVING REDUCED EFFECTIVE SUBSTRATE RESISTIVITY AND ASSOCIATED METHODS 09/551187 Pending US SEMICONDUCTOR DEVICE HAVING REDUCED EFFECTIVE SUBSTRATE RESISTIVITY AND ASSOCIATED METHODS 6162702 09/334835 Granted US SELF-SUPPORTING ULTRATHIN SILICON WAFER PROCESS 09/303270 Pending US POWER MOS DEVICE WITH INCREASED CHANNEL WIDTH AND PROCESS FOR FORMING SAME 09/765177 Pending US POWER MOS DEVICE WITH INCREASED CHANNEL WIDTH AND PROCESS FOR FORMING SAME 09/450872 Pending US EMITTER BALLAST RESISTOR WITH ENHANCED BODY EFFECT TO IMPROVE THE SHORT CIRCUIT WITHSTAND CAPABILITY OF POWER DEVICES 09/339356 Pending US BACKMETAL DRAIN TERMINAL WITH LOW STRESS AND THERMAL RESISTANCE 6188105 09/283531 Granted US HIGH DENSITY MOS-GATED POWER DEVICE AND PROCESS FOR FORMING SAME 09/260411 Pending US MOS-GATED DEVICE HAVING A BURIED GATE AND PROCESS FOR FORMING SAME 09/318334 Pending US TRENCH-GATED DEVICE HAVING TRENCH WALLS FORMED BY SELECTIVE EPITAXIAL GROWTH AND PROCESS FOR FORMING DEVICE 09/314323 Pending US MOS-GATED POWER DEVICE HAVING EXTENDED TRENCH AND DOPING ZONE AND PROCESS FOR FORMING SAME 09/726682 Pending US MOS-GATED POWER DEVICE HAVING EXTENDED TRENCH AND DOPING ZONE AND PROCESS FOR FORMING SAME 09/345930 Pending US POWER SEMICONDUCTOR MOUNTING PACKAGE CONTAINING BALL GRID ARRAY 09/525182 Pending US POWER TRENCH TRANSISTOR DEVICE SOURCE REGION FORMATION USING SILICON SPACER 09/624533 Pending US POWER MOS DEVICE WITH BURIED GATE 09/654845 Pending US POWER SEMICONDUCTOR DEVICE WITH HIGH AVALANCHE CAPABILITY 09/718219 Pending US PROCESS FOR CONTROLLING LIFETIME IN A P-I-N DIODE AND FOR FORMING DIODE WITH IMPROVED LIFETIME CONTROL 09/689939 Pending US MOS-GATED POWER DEVICE HAVING SEGMENTED TRENCH AND EXTENDED DOPING ZONE AND PROCESS FOR FORMING SAME 09/502712 Pending US MOS-GATED DEVICE HAVING ALTERNATING ZONES OF CONDUCTIVITY 09/665,850 Pending US SELF-ALIGNED PROCESS FOR FABRICATING POWER MOSFET WITH SPACER-SHAPED TERRACED GATE 09/603605 Pending US SOFT RECOVERY POWER DIODE AND RELATED METHOD 60/198692 Pending US QUASI-RESONANT CONVERTER 09/664024 Pending US INTEGRATED CIRCUIT DEVICE INCLUDING A DEEP WELL REGION AND ASSOCIATED METHODS 60/219858 Pending US PRODUCED BY USING A FULLY SELF-ALIGNED BODY IMPLANT PROCESS 4994871 07/279392 Granted US INSULATED GATE BIPOLAR TRANSISTOR WITH IMPROVED LATCHUP CURRENT LEVEL AND SAFE OPERATING AREA 5134321 07/644569 Granted US POWER MOSFET AC POWER SWITCH EMPLOYING MEANS FOR PREVENTING CONDUCTION OF BODY DIODE 4634473 773772 Granted US METHOD FOR FABRICATING A RADIATION HARDENED OXIDE HAVING STRUCTURAL DAMAGE 4998151 337684 Granted US POWER FIELD EFFECT DEVICES HAVING SMALL CELL SIZE AND LOW CONTACT RESISTANCE AND METHOD OF FABRICATION 4587713 582601 Granted US METHOD FOR MAKING VERTICAL MOSFET WITH REDUCED BIPOLAR EFFECTS 4648174 698495 Granted US METHOD OF MAKING HIGH BREAKDOWN VOLTAGE SEMICONDUCTOR DEVICE 4927772 358057 Granted US HIGH BREAKDOWN VOLTAGE SEMICONDUCTOR DEVICE AND METHOD OF FABRICATION 4675978 773771 Granted US METHOD FOR FABRICATING A RADIATION HARDENED OXIDE 6080614 08/885877 Granted US METHOD OF MAKING A MOS-GATED SEMICONDUCTOR DEVICE WITH A SINGLE DIFFUSION 09/449487 Pending US METHOD OF MAKING A MOS-GATED SEMICONDUCTOR DEVICE WITH A SINGLE DIFFUSION 60/234563 Pending US CONTROLLING SILICON TRENCH PROFILES BY INCREMENTAL INCREASES IN OXYGEN FLOWS 5103290 07/367525 Granted US HERMETIC PACKAGE HAVING A LEAD EXTENDING THROUGH AN APERTURE IN THE PACKAGE LID AND PACKAGED SEMICONDUCTOR CHIP 5446316 08/217801 Granted US METHOD OF PACKAGING A SEMICONDUCTOR DEVICE 5577656 08/462856 Granted US METHOD OF PACKAGING A SEMICONDUCTOR DEVICE 5473193 08/177974 Granted US PACKAGE FOR PARALLEL SUBELEMENT SEMICONDUCTOR DEVICES 08/759865 Pending US A METHOD OF METALIZING A SEMICONDUCTOR POWER DEVICE CERAMIC MEMBER 5995349 08/944513 Granted US PROTECTION DEVICE FOR SOLID STATE SWITCHED POWER ELECTRONICS 6060795 09/040112 Granted US SEMICONDUCTOR POWER PACK 4545109 459756 Granted US METHOD OF MAKING A GALLIUM ARSENIDE FIELD EFFECT TRANSISTOR 4516143 579229 Granted US SELF-ALIGNED POWER MOSFET WITH INTEGRAL SOURCE BASE SHORT A 4567641 650314 Granted US METHOD OF FABRICATING SEMI- CONDUCTOR DEVICE HAVING A DIFFUSED REGION OF REDUCED LENGTH 449321 Pending US LATERAL INSULATED GATE RECTIFIER STRUCTURES 449322 Pending US BIDIRECTIONAL INSULATED GATE RECTIFIER STRUCTURES AND METHOD 464161 Granted US BIDIRECTIONAL INSULATED GATE RECTIFIER STRUCTURES AND METHOD 4862242 807612 Granted US SEMICONDUCTOR WAFER WITH AN ELECTRICALLY ISOLATED SEMICONDUCTOR 726749 Pending US INSULATED GATE SEMICONDUCTOR DEVICE 4516143 579229 Granted US SELF-ALIGNED POWER MOSFET WITH INTEGRAL SOURCE-BASE SHORT AND METHODS OF MAKING 4595428 567708 Granted US METHOD FOR PRODUCING HIGH ASPECT RATIO HOLLOW DIFFUSED REGIONS IN A SEMICOND- UCTOR BODY AND DIODE PRODUCED THEREBY 4546375 439563 Granted US VERTICAL IGFET WITH INTERNAL GATE AND METHOD FOR MAKING SAME 09/829,634 Pending US POTTED TRANSDUCER ARRAY WITH MATCHING NETWORK IN A MULTIPLE PASS CONFIGURATION 09/799,845 Pending US POWER TRENCH TRANSISTOR DEVICE SOURCE REGION FORMATION USING SILICON SPACER 09/839,374 Pending US QUASI-RESONANT CONVERTER 09/815,372 Pending US EDGE TERMINATION FOR SILICON POWER DEVICES 09/844,347 Pending US POWER MOSFET AND METHOD FOR FORMING SAME USING A SELF-ALIGNED BODY IMPLANT 08/310,041 Pending US FET, IGBT AND MCT STRUCTURES TO ENHANCE OPERATING CHARACTER 5577656 462856 Granted US METHOD OF PACKAGING A SEMICONDUCTOR DEVICE 09/731,169 Pending US MOS-GATED POWER DEVICE WITH DOPED POLYSILICON BODY AND PROCESS FOR FORMING SAME

[0026] following claims. 

What is claimed is:
 1. An improved MOS-gated power device on a substrate having an upper layer, said substrate comprising in said upper layer doped monocrystalline silicon of a first conduction type and including a doped well region of a second conduction type, said substrate further comprising at least one heavily doped source region of said first conduction type disposed in said well region at an upper surface of said upper layer, a gate region comprising a conductive material electrically insulated from said source region by a dielectric material, a patterned interlevel dielectric layer on said upper surface overlying said gate and source regions, and a heavily doped drain region of said first conduction type; wherein the improvement comprises: At least one body region of said second conduction type disposed in said well region at said upper surface of said substrate, said body region comprising heavily doped polysilicon.
 2. The device of claim 1 wherein said upper layer is an epitaxial layer.
 3. The device of claim 1 wherein said first conduction type is N and said second conduction type is P.
 4. The device of claim 1 wherein said conductive material in said gate region comprises doped polysilicon.
 5. The device of claim 1 wherein said dielectric material in said gate region comprises silicon dioxide.
 6. The device of claim 1 comprising a trench MOS-gated device.
 7. The device of claim 1 comprising a vertical planar MOS device.
 8. The device of claim 1 comprising a lateral MOSFET.
 9. The device of claim 6 wherein said device comprises a plurality of extended trenches.
 10. The device of claim 9 wherein said plurality of extended trenches have an open-cell striped topology or a closed-cell striped topology.
 11. The device of claim 1 selected from the group consisting of a power MOSFET, an insulated gate bipolar transistor, and an MOS-controlled thyristor.
 12. A process for forming an MOS-gated power device comprising: providing a substrate having an upper layer, said substrate comprising in said upper layer doped monocrystalline silicon of a first conduction type and including a doped well region of a second conduction type, said substrate further comprising at least one heavily doped source region of said first conduction type disposed in said well region at an upper surface of said upper layer, a gate region comprising a conductive material electrically insulated from said source region by a dielectric material, a heavily doped drain region of said first conduction type, and a patterned interlevel dielectric layer on said upper surface overlying said gate and source regions; forming a body mask on said substrate, and selectively removing portions of said source region and underlying well region remotely disposed from said gate region, thereby forming at least one body hollow in said substrate; removing said body mask, and forming a blanket layer of heavily doped polysilicon of said second conduction type over said substrate and said interlevel dielectric layer, said polysilicon filling said body hollow; selectively removing portions of said polysilicon blanket layer from said source region and said interlevel dielectric layer, leaving polysilicon filling said body hollow, said hollow filled with heavily doped polysilicon comprising a body region; depositing over said upper surface and interlevel dielectric layer a source metal layer in electrical contact with said source and body regions; and forming a drain metal layer in contact with said drain region in said substrate.
 13. The process of claim 12 wherein said upper layer is an epitaxial layer.
 14. The process of claim 12 wherein said first conduction type is N and said second conduction type is P.
 15. The process of claim 12 wherein said conductive material in said gate region comprises doped polysilicon and said dielectric material in said gate region comprises silicon dioxide.
 16. The process of claim 12 wherein said power device comprises a trench MOS-gated device.
 17. The process of claim 12 wherein said power device comprises a planar MOS device.
 18. The process of claim 12 wherein said power device comprises a lateral MOSFET.
 19. The process of claim 16 wherein said device comprises a plurality of extended trenches.
 20. The process of claim 19 wherein said plurality of extended trenches have an open-cell striped topology or a closed-cell striped topology.
 21. The process of claim 12 wherein said power device is selected from the group consisting of a power MOSFET, an insulated gate bipolar transistor, and an MOS-controlled thyristor. 